High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM

Significant challenges are posed in the design of routers and switches by explosive growth internet traffic stringent requirements for high availability research area computer networks. Ensuring both performance system is crucial. To achieve this, recent advancements have turned to utilization non-volatile memories, such as magnetic RAM (MRAM) phase-change memory (PCM), routing lookup tables packet buffers switches. However, use memories show limitations scaling with respect bandwidth capacity. With increasing clock speed IO bus, high-capacity like PCM exhibit limited scalability since accessing cells array does not significant improvement. Meanwhile, attempts enhance capacity low-access-latency spin-transfer torque MRAM (STT-MRAM) through smaller cell sizes result an adverse impact on write time. The goal this study a buffer that can provide ensure availability. multi-retention time MRAM-based presented, along mapping method, which aims overcome challenge while ensuring two-tier (TT-PB) structure implements small/fast combined large/slow MRAM, outperforms baseline MRAM/PCM hybrid memory-based up 16% 58% 1.6 3.2 GHz bus clocks. For input, internet-mix utilized depict realistic traffic. Moreover, proposed latency-aware (MR-PB) consists short long retention partitions. It identifies buffering latency demands various packets writes into partitions sufficient accommodate required latencies, thereby achieving optimal each packet. scheme, additional speedup 5.27% achieved over TT-PB.